#-- Synplicity, Inc. #-- Version 6.0 #-- Project file c:\decss\verilog\CSTable_5.prj #-- Written on Wed Mar 07 16:01:55 2001 #add_file options add_file -verilog "decss.v" add_file -verilog "cstable_5.v" add_file -verilog "cstable_1.v" add_file -verilog "cstable_4.v" add_file -verilog "cstable_3.v" add_file -verilog "cstable_2.v" #implementation: "rev_1" impl -name rev_1 #device options set_option -technology FLEX10K set_option -part EPF10K10 set_option -package LC84 set_option -speed_grade -3 #compilation/mapping options set_option -default_enum_encoding default set_option -symbolic_fsm_compiler 1 set_option -resource_sharing 1 #map options set_option -frequency 0.000 set_option -domap 1 set_option -cliquing 1 set_option -pipe 0 #simulation options set_option -write_verilog 0 set_option -write_vhdl 0 #automatic place and route (vendor) options set_option -write_apr_constraint 1 #set result format/file last project -result_file "rev_1/cstable_2.edf"