module CSTable_3 ( Clk, Resetn, Addr, Data ) /* synthesis black_box LPM_WIDTH=8 LPM_WIDTHAD=9 LPM_TYPE="LPM_RAM_DQ" */ ; input Clk, Resetn; input [8:0] Addr; output [7:0] Data; reg [7:0] Data; // FOR SIMULATION, NOT SYNTH reg [7:0] cell [0:511]; integer i; initial begin $display("\tInitializing CSTable_3 for Simulation.."); $readmemh("CSTable_3.txt",cell); end // initial always @(posedge Clk or negedge Resetn) begin if (!Resetn) begin $display("Reset CSTable_3 Rom"); Data <= 32'h 0; end else begin Data <= cell[Addr]; end end // always endmodule