---------------------------------------------------------------- | | | | | Zilog | | | | ZZZZZZZ 88888 | | Z 8 8 | | Z 8 8 | | Z 88888 | | Z 8 8 | | Z 8 8 | | ZZZZZZZ 88888 | | | | Z8601/02/03/11/12/13 Single-Chip MICROCOMPUTER | | Instruction Set Summary | | | | | | | | | | _________ _________ | | _| \__/ |_ | | +5V |_|1 40|_| P36 --> | | _| |_ | | <-- XTAL2 |_|2 39|_| P31 <-- | | _| |_ | | --> XTAL1 |_|3 38|_| P27 <--> | | _| |_ | | <-- P37 |_|4 37|_| P26 <--> | | _| |_ | | --> P30 |_|5 36|_| P25 <--> | | _____ _| |_ | | --> RESET |_|6 35|_| P24 <--> | | _ _| |_ | | <-- R/W |_|7 34|_| P23 <--> | | __ _| |_ | | <-- DS |_|8 33|_| P22 <--> | | __ _| |_ | | <-- AS |_|9 Z8601 32|_| P21 <--> | | _| Z8603 |_ | | <-- P35 |_|10 Z8611 31|_| P20 <--> | | _| Z8613 |_ | | GND |_|11 30|_| P33 <-- | | _| |_ | | --> P32 |_|12 29|_| P34 --> | | _| |_ | | <--> P00 |_|13 28|_| P17 <--> | | _| |_ | | <--> P01 |_|14 27|_| P16 <--> | | _| |_ | | <--> P02 |_|15 26|_| P15 <--> | | _| |_ | | <--> P03 |_|16 25|_| P14 <--> | | _| |_ | | <--> P04 |_|17 24|_| P13 <--> | | _| |_ | | <--> P05 |_|18 23|_| P12 <--> | | _| |_ | | <--> P06 |_|19 22|_| P11 <--> | | _| |_ | | <--> P07 |_|20 21|_| P10 <--> | | |______________________| | | | | | | | | | | | | | |Written by Jonathan Bowen | | Programming Research Group | | Oxford University Computing Laboratory | | 8-11 Keble Road | | Oxford OX1 3QD | | England | | | | Tel +44-865-273840 | | | |Created June 1982 | |Updated April 1985 | |Issue 1.1 Copyright (C) J.P.Bowen 1985| ---------------------------------------------------------------- ---------------------------------------------------------------- |Mnemonic|Op|CZSVDH|#|Description |Notes | |--------+--+------+-+-----------------------+-----------------| |ADC d,s |1X|****0*|a|Add with Carry |d=d+s+C | |ADD d,s |0X|****0*|a|Add |d=d+s | |AND d,s |5X|-**0--|a|Logical AND |d=d&s | |CALL d |D4|------|b|Call subroutine |-[SP]=PC,PC=d | |CCF |EF|*-----|c|Complement Carry Flag |C=~C | |CLR d |B0|------|d|Clear |d=0 | |COM d |60|-**0--|d|Complement |d=~d | |CP d,s |AX|****--|a|Compare |d-s | |DA d |40|***?--|d|Decimal Adjust |d=BCD format | |DEC d |00|-***--|d|Decrement |d=d-1 | |DECW d |80|-***--|d|Decrement Word |d=d-1 | |DI |8F|------|c|Disable Interrupts |IMR<7>=0 | |DJNZ r,d|rA|------|e|Dec. and Jump Non-Zero |r=r-1, if r<>0 JR| |EI |9F|------|c|Enable Interrupts |IMR<7>=1 | |INC d |rE|-***--|f|Increment |d=d+1 | |INCW d |A0|-***--|d|Increment Word |d=d+1 | |IRET |BF|******|c|Interrupt Return |{F,PC}=[SP]+,EI | |JP c,d |cD|------|g|Conditional Jump |If c PC=d | |JR c,d |cB|------|h|Cond. Jump Relative |If c PC=PC+d | |LD d,s |rC|------|i|Load |d=s | |LDC d,s |C2|------|j|Load |d=s | |LDCI d,s|C3|------|k|Load and Increment |d=s,r=r+1,rr=rr+1| |LDE d,s |82|------|j|Load |d=s | |LDEI d,s|83|------|k|Load and Increment |d=s,r=r+1,rr=rr+1| |NOP |FF|------|c|No Operation | | |OR d,s |4X|-**0--|a|Logical inclusive OR |d=dvs | |POP d |50|------|d|Pop |d=[SP]+ | |PUSH s |70|------|d|Push |-[SP]=s | |RCF |CF|------|c|Reset Carry Flag |C=0 | |RET |AF|------|c|Return |PC=[SP]+ | |RL d |90|****--|d|Rotate Left |d=d<- | |RLC d |10|****--|d|Rotate Left Circular |d={C,d}<- | |RR d |E0|****--|d|Rotate Right |d=->d | |RRC d |C0|****--|d|Rotate Right Circular |d=->{C,d} | |SBC d,s |3X|****1*|a|Subtract with Carry |d=d-s-C | |SCF |DF|1-----|c|Set Carry Flag |C=1 | |SRA d |D0|***0--|d|Shift Right Arithmetic |d=d/2 | |SRP s |31|------|k|Set Register Pointer |RP=s | |SUB d,s |2X|****1*|a|Subtract |d=d-s | |SWAP d |F0|?**?--|d|Swap nibbles |d<0:3><->d<4:7> | |TCM d,s |6X|-**0--|a|Test Complement Memory |{~d}&s | |TM d,s |7X|-**0--|a|Test Memory |d&s | |XOR d,s |BX|-**0--|a|Logical Exclusive OR |d=dxs | |-----------+------+-+-----------------------------------------| | FLAGS |-/*/ | |Unaffected/affected/ |Register 252 | | |0/1/? | |reset/set/unknown. | | | C |C | |Carry flag |Bit 7 | | Z | Z | |Zero flag |Bit 6 | | S | S | |Sign flag |Bit 5 | | V | V | |Overflow flag |Bit 4 | | D | D | |Decimal-adjust flag |Bit 3 | | H | H| |Half-carry flag |Bit 2 | | F2 | | |User flag 2 |Bit 1 | | F1 | | |User flag 1 |Bit 0 | |--------------------+-----------------------------------------| | c = XXXXB |Condition |Top nibble of Op | | 1000B |Always true |If true | | C = 0111B |Carry (C=1) |If C=1 | | NC = 1111B |No carry (C=0) |If C=0 | | Z = 0110B |Zero (Z=1) |If Z=1 | | NZ = 1110B |Not zero (Z=0) |If Z=0 | | PL = 1101B |Plus (S=0) |If S=0 | | MI = 0101B |Minus (S=1) |If S=1 | | OV = 0100B |Overflow (V=1) |If V=1 | | NOV = 1100B |No overflow (V=0) |If V=0 | | EQ = 0110B |Equal (Z=1) |If Z=1 | | NE = 1110B |Not equal (Z=0) |If Z=0 | | GE = 1001B |Greater than or equal |If SxV=0 | | LT = 0001B |Less than |If SxV=1 | | GT = 1010B |Greater than |If Zv{SxV}=0 | | LE = 0010B |Less than or equal |If Zv{SxV}=1 | | UGE = 1111B |Unsigned greater/equal |If C=0 | | ULT = 0111B |Unsigned less than |If C=1 | | UGT = 1011B |Unsigned greater than |If CvZ=0 | | ULE = 0011B |Unsigned less/equal |If CvZ=1 | | 0000B |Never true |If false | ---------------------------------------------------------------- ---------------------------------------------------------------- |Mnemonic |Description | |--------------------+-----------------------------------------| | DA |Direct address | | IM |Immediate | | Ir |Indirect working register | | IR |Indirect register or Ir | | Irr |Indirect working register pair address | | IRR |Indirect register pair or Irr | | r |Working register address | | R |Register or r | | RA |Relative address | | rr |Working register pair address | | RR |Register pair or rr | | X |Indexed address | |--------------------+-----------------------------------------| | d |Destination location or contents | | s |Source location or contents | | # |Addressing mode type(s) | | #a |X=2-7: d,s=r,r/r,Ir/R,R/R,IR/R,IM/IR,IM | | #b |Op=D4/D6: d=IRR/DA (CALL)| | #c |No operands | | #d |Op=X0/X1: d=R/IR | | #e |Op=rA: r=0-F, d=RA (DJNZ)| | #f |Op=rE/20/21: d=r/R/IR (INC)| | #g |Op=cD/30: d=DA/IRR (JP)| | #h |Op=cB: d=RA (JR)| | #i |Op=rC/r8/r9/C7/ d,s=r,Im/r,R/R,r/r,X/ | | | D7/E3/E4/E5/ X,r/r,Ir/R,R/R,IR/ | | | E6/E7/F3/F5: R,Im/IR,Im/Ir,r/IR,R (LD)| | #j |Op=C2/D2: d,s=r,Irr/Irr,r (LDC/LDE)| | #k |Op=C3/D3: d,s=Ir,Irr/Irr,Ir (LDCI/LDEI)| |--------------------+-----------------------------------------| | 0 - 255 |Register file addresses|00H-FFH | | P0 = 0 |Port 0 |00H R/W | | P1 = 1 |Port 1 |01H R/W | | P2 = 2 |Port 2 |02H R/W | | P3 = 3 |Port 3 |03H R W | | 4 - 127 |General purpose regs. |04H-7FH R/W | | 128 - 239 |Unused |80H-EFH | | SIO = 240 |Serial I/O |F0H R/W | | TMR = 241 |Timer mode |F1H R/W | | T1 = 242 |Timer/counter 1 |F2H R/W | | PRE1 = 243 |T1 prescaler |F3H WO | | T0 = 244 |Timer/counter 0 |F4H R/W | | PRE0 = 245 |T0 prescaler |F5H WO | | P2M = 246 |Port 2 mode |F6H WO | | P3M = 247 |Port 3 mode |F7H WO | | P01M = 248 |Ports 0-1 mode |F8H WO | | IPR = 249 |Interrupt priority reg.|F9H WO | | IRQ = 250 |Interrupt request reg. |FAH R/W | | IMR = 251 |Interrupt mask reg. |FBH R/W | | FLAGS = 252 |Program control flags |FCH R/W | | RP = 253 |Register pointer |FDH R/W | | SPH = 254 |Stack pointer high byte|FEH R/W | | SPL = 255 |Stack pointer low byte |FFH R/W | |--------------------+-----------------------------------------| | + |Add | | - |Subtract | | * |Multiply | | / |Divide | | & |Logical AND | | ~ |Logical NOT | | v |Logical inclusive OR | | x |Logical exclusive OR | | <- |Rotate left | | -> |Rotate right | | <-> |Exchange | | [ ] |Indirect addressing | | [ ]+ -[ ] |Auto-increment/decrement indirect address| | < > < : > |Bit number/range | | { } |Combination of operands | |--------------------+-----------------------------------------| | Z8601 |Single-chip microcomputer with 2K ROM | | Z8602 |Development device with memory interface | | Z8603 |Prototyping device with EPROM interface | | Z8611 |Single-chip microcomputer with 4K ROM | | Z8612 |Development device with memory interface | | Z8613 |Prototyping device with EPROM interface | ----------------------------------------------------------------