DOCUMENTATION CLARIFICATION FOR MC68040: 2E42K MASK SET MC68EC040 & MC68LC040: 2E71M MASK SET 1.) If a locked access hits in the data cache, but the data cache is disabled, when the data cache is re-enabled, the next non-locked access that misses in the data cache will not be cached. This problem can be avoided by invalidating the data cache when it has been disabled. 2.) To avoid the possibility of momentary bus contention of address and attribute lines, a bus arbiter must insure that there is at least one clock after the 68040's BG* is negated and before the new master's BG* is asserted. 3.) If a locked access (TAS/CAS instruction) references a dirty entry in the data cache, it invalidates the proper cache entry and pushes this data onto the data bus. However, the 68040 asserts the LOCK* signal during the bus cycle for the push and keeps the signal asserted until the completion of the locked access. Therefore, to avoid this case for systems where these instructions are used for control of semaphores, have the semaphores located in cache-inhibited space. 4.) If a MOVE16 instruction has both source & destination addresses hitting in the same copyback mode cache line (effectively a cache line push), the source is dirty in the cache line, and the access is write- protected, then the dirty cached data may be lost. 5.) MOVE16 (Ax)+,(Ay)+ where Ax=Ay is functionally the same as MOVE16 (Ax),(Ay)+. The address register only gets incremented once and the line is copied over itself instead of copied into the next line. 6.) A bus error on a cache line push (TEA* asserted) which is initiated after the IPEND* signal is asserted to signal pending interrupt processing may cause a Spurious Interrupt Exception instead of an Access Fault Exception. This is a non-recoverable bus error case which may be detected in the Spurious Interrupt Exception handler routine and dispatched to the appropriate system error routine. 7.) If a write in copyback space is misaligned so that the operand request spans two cache lines, and a bus error (TEA* asserted) is asserted on the fetch of the second, third or fourth longword of the second cache line (i.e. addresses xxx4, xxx8 or xxxC), then the bus error may not be recoverable without loss of data. Specifically, if subsequent instructions also write to an address that overlaps the misaligned operand used by the original instruction, then the data written by any number of these subsequent instructions may be lost. For systems which wish to recover from physical bus errors of this type, insert a NOP instruction after the instruction which performs the original misaligned write. 8.) If a line transfer is burst inhibited by asserting the TBI* signal, three additional longword bus cycles are run by the 68040 to complete the original line transfer. Within the tenure of these fake-burst transfers, assertion of TA* during the BCLK cycles in which TS* is asserted will result in improper sequencing of the burst inhibited line transfer. In all other cases the 68040 ignores the TA* input signal when the TS* output is asserted. 9.) Bus Snooping operation requires that accesses to shared memory space by either the 68040 or an alternate master must be aligned (i.e. misaligned data cache reads into a shared memory space may result in operands corrupted by intervening snoop cycles). When shared memory accesses are controlled via a software semaphore technique, the semaphore locations should not be misaligned in memory. 10.) (MC68040 & MC68LC040 only) If an A-line, Illegal, CHK, or Unimplemented Floating Point instruction is in the last 16 bits of a page and the next page does not exist (or is nonresident with pdt=0), the proper exception is not reported. Instead of reporting the proper exception, the 68040 attempts to prefetch the next instruction on the missing page, and an instruction ATC fault is reported with the fault address showing the first word of the missing page and the program counter showing the address of the instruction on the preceding page. 11.) (MC68040 & MC68LC040 only) If an MMU tablewalk occurs during exception stacking for a write access which was bus errored (TEA* asserted), the access error stack frame will incorrectly indicate valid WB1 and WB3 with the same address and data. To recover from the bus error and avoid a duplicate write, the access error handler must detect this case and discard the WB1 write-back. Discarding the WB1 write-back in this way will not compromise data integrity, nor will it discard intentional multiple writes to serialized space. 12.) (MC68040 & MC68LC040 only) MOVE16 write accesses to a memory page marked invalid may improperly invalidate a dirty cache line. To avoid this case set the physical address field in all invalid MMU descriptors to a physical page which is NEVER mapped in the system. A MOVE16 write fault will never find a matching line in the cache to (incorrectly) invalidate. DOCUMENTATION CLARIFICATION CHANGE HISTORY Rev A: MC Maskset (2E71M) corrects #I1 - #I5, #H1, half of #E2, #E3 - #E4, #G2 MC Maskset (2E42K) corrects #I1 - #I5, #H1, half of #E2, #E3 - #E4, #G2, #F1 - #F6