MAYER's SV738 X'press I/O MAP version 1.4 Last edition Sunday 25-Apr-93. This I/O documentation was written 1991 by MAYER of WC HAKKERS. It consists of gathered info about the MSX computer SV738 X'Press (here upgraded to MSX 2 by changing ROM and VRAM - see documentation about MSX-2 upgrading). Thanks to Henrik Gilvad (Denmark) for info about the MSX-2 MVDP and the MSX-2 ROMs, to Pål F Hansen (Norway) for VRAM info and to Jonas Lindström (Sweden) for some MVDP info. This documentation is not completed, but it includes the most important things when dealing with I/O ports on a MSX. I do not take any responsibility for changes done by anybody else later in the text. If You change anything I advise You to leave a note on the last page about the change. Copyright (c) 1991 by WC HAKKERS This text may not be sold, included in commercial software/hardware or firmware packages and it may not be duplicated by any means without the authors permission. This text is shareware; You might copy it an spread it as long as You doesn't sell the copies. So if You spread this documentation, leaving this page intact and without changes, You have my permission to duplicate it. MAYER ----- In the examples, the BASIC variable A corresponds to the CPU register [a]. The BASIC variable B corresponds to the CPU register [b]. The BASIC variable HL corresponds to the CPU register pair [hl]. In the I/O port page, Port numbers are in hex. NC= Not connected R= read W= Write I/O R/W: Note: Chip/Name: Function: port: Not connected on SV738 X'press: 00-3F *** Unspecified *** 40-7B *** Reserved *** 7C NC - FM-PAK (MSX MUSIC) reg. select 7D NC - FM-PAK (MSX MUSIC) data I/O 7E-7F *** Reserved *** Connected on SV738 X'press: 80 R/W 1 I8251 (ACIA) Data RS232 81 R/W 2 I8251 (ACIA) Status/Command RS232 82 R 3 RS232 Status for CTS,Timer/counter2,RI,CD 82 W 4 RS232 Interrupt mask register 83 R RS232 ?Clock 0,1,2 read? 83 W RS232 ?Receive ready interrupt enable? 84 R/W 5 I8253 (Baud gener.) Counter 0 Receive clock 85 R/W 6 I8253 (Baud gener.) Counter 1 Transmit clock 86 R/W 7 I8253 (Baud gener.) Counter 2 Used by programs 87 W 8 I8253 (Baud gener.) Mode register 88 ? ? ?Modem enable? 89-8B NC Reserved for MSX-1 MVDP 9938 adaptor 8C-8D NC Reserved for modem 90 R - ULA5RA087 Centronic BUSY state (bit 1=1) 90 W - ULA5RA087 Centronic STROBE output (bit 0=0) 91 W - ULA5RA087 Centronic Printer Data (characters out ASCII) 92-97 NC *** Reserved *** 98 R 9 9918,9929,9938,9958,9978 VRAM data READ 98 W 10 9918,9929,9938,9958,9978 VRAM data WRITE 99 R 11 9938,9958,9978,9929 VDP status (Interrupt,Spr Conc,5th) 99 W 12 9938,9958,9978,9929 VDP address setup/Register write 9A W 12b MVDP colour palette registers data write (2 bytes) 9B ? - MVDP Register data 9C-9F NC *** Reserved *** A0 W 13 I AY-3-8910 PSG Register select A1 W 14 I AY-3-8910 PSG Data write A2 R 15 I AY-3-8910 PSG Data read A3-A7 NC *** Reserved *** A8 R 16 I 8255A/ULA9RA041 Port A Memory slot reister Read A8 W 17 I 8255A/ULA9RA041 Port A Memory slot reister Write A9 R 18 I 8255A/ULA9RA041 Port B Keyboard column inputs A9 W 18 I 8255A/ULA9RA041 Port B AA R 19 I 8255A/ULA9RA041 Port C Get Kbd Row sel,LED,CASo,CASm AA W 19 I 8255A/ULA9RA041 Port C Set Kbd Row sel,LED,CASo,CASm AB R 20 I 8255A/ULA9RA041 Mode AB W 20 I 8255A/ULA9RA041 Mode select and I/O setup of A,B,C AC-AF *** Reserved *** B0-B3 NC - External 8255 (SONY DataRamPack) B4 W 21 RP 5C01 (Not in 738) RTC Register select B5 R/W 21 RP 5C01 (Not in 738) RTC data B6-B7 NC *** Reserved *** Not connected on SV738 X'press: B8-BB NC - SANYO Light pen interface BC-BF NC - VHD control C0-C1 NC - MSX audio (MSX MUSIC again?) C2-C7 *** Reserved *** C8-CF ? - MSX Interface (??) D0-D7 ? - External Floppy Disk Controller D8-DB Kanji ROM for Chinese characters (Not included in European vers) DC-F4 *** Reserved *** F5 ? - System control F6 ? - colour bus F7 W - Audio/Video control F8-FB *** Reserved *** FC-FF R/W 22 Memory mapper 100-FFFF *** Unspecified on SV 738 X'press *** (can be used via reg [bc] only). Notes ACIA (Asynchronous Communication Interface Adapter) Note 1 - I/O port 80h This port holds the byte received from RS232. This port is also used to send bytes to RS232. Note 2 - I/O port 81h Input from this port will give the status of the RS232 interface. Bit: Function: 0 TxRDY; Transmit Ready 1 RxRDY; Receive Ready (1 when received byte is enable for CPU). 2 TxEMPTY; Transmit buffer Empty 3 PE; Parity Error if 1 4 OE; Overrun Error if 1 (CPU has not received character) 5 FE; Framing Error if 1 (ASYNC only, STOP BIT not valid) 6 SYNDET/BRKDET; SYNC/BREAK found 7 DSR; Data Set Ready Output to this port will set parameters in the i8251 ACIA. Directly after a RESET command (see command format below), the MODE SETUP byte may be written: ; -- MODE SETUP -- word EQU 00001100b ; 8 data bits ; xxxx00xxb = 5 bits ; xxxx01xxb = 6 " ; xxxx10xxb = 7 " ; xxxx11xxb = 8 " ;---- paren EQU 00000000b ; No parity ; xxx0xxxxb = Disable parity ; xxx1xxxxb = Enable " ;---- parity EQU 00000000b ; Odd ; xx0xxxxxb = Odd parity generation/Check ; xx1xxxxxb = Even parity generation/Check ;---- STOP EQU 01000000b ; 1 Stop bit ; 00xxxxxxb = Invalid ; 01xxxxxxb = 1 Bit ; 10xxxxxxb = 1.5 Bit ; 11xxxxxxb = 2 Bit ;---- baudfact EQU 00000010b ; x16 ; xxxxxx00b = SYNC MODE ; xxxxxx01b = 1 * CLK ; xxxxxx10b = 1/16 * CLK ; xxxxxx11b = 1/64 * CLK ;---- After the MODE SETUP byte has been written, the COMMAND SETUP BYTE may be written: ; -- COMMAND SETUP -- tx EQU 00000001b ; Transmit enable/Disable ; xxxxxxx0b ; Transmit disable ; xxxxxxx1b ; Transmit enable dtr EQU 00000010b ; Set Data Terminal Ready/Not Ready ; xxxxxx0xb ; Data Terminal Not Ready ; xxxxxx1xb ; Data Terminal Ready rx EQU 00000100b ; Receive enable, 0= Disable ; xxxxx0xxb ; Receive Disable ; xxxxx1xxb ; Receive enable brk EQU 00001000b ; Break/Normal operation ; xxxx0xxxb ; Normal Operation ; xxxx1xxxb ; Send Break (TxD=Low) err_reset EQU 00010000b ; Error reset ; xxx0xxxxb ; No operation ; xxx1xxxxb ; Reset error flags PE,OE and FE rts EQU 00100000b ; Set/reset Request To Send ; xx0xxxxxb ; _RTS = 1 (No Request To Send) ; xx1xxxxxb ; Request to send reset EQU 01000000b ; Internal reset ; x0xxxxxxb ; No operation ; x1xxxxxxb ; RESET and wait for MODE instr.input Hunt EQU 10000000b ; Enter Hunt mode ; 0xxxxxxxb ; No operation ; 1xxxxxxxb ; Enable search for SYNC character An example routine to initialize the i8251A (for write) is shown below: xor a ; Make sure i8251 is in COMMAND mode out (081h),a ; Sync mode out (081h),a ; Dummy sync char out (081h),a ; Dummy sync char inc a out (088h),a ; mdm enable ld a,reset out (081h),a ; Set i8251 in MODE state ld a,word+stop+paren+parity+baudfact out (081h),a nop ; Now, i8251 is in COMMAND state ld a,err_reset ; Reset error flags out (081h),a ld a,dtr+rx+tx out (081h),a nop in a,(081h) ; Read status ret An example routine to receive a byte to [a] from RS232 is shown below: ; Get RS232 -> [a] recv: ld a,dtr+rx+err_reset out (081h),a rec2: in a,(081h) and 00000010b ; Mask in RxRDY jr z,rec2 ; Jp if no data in a,(080h) ret Note 3 - Input from port 82h will get the status of CTS,Timer/counter2, RingIndicator and Carrier detect. bit Expl. 0 = CD - Carrier detect, 0=Active, 1=Not active 1 = RI - Ring indicator, 0=Active, 1=Not active (*) 6 = Timer/counter2 output from i8253 7 = CTS - Clear to send, 0=Active, 1=Not active Note 4 - Output to port 82h will set the interrupt mask (interrupt enable/disable, bits: 0=Enable, 1=Disable). bit Expl. 0 = RxReady Receive data ready 1 = TxReady Transmit data ready (*) 2 = Sync/Break found (*) 3 = Timer interrupt from i8253 channel 2 (*) (*) = Not connected, see engineering document #STM-738-006 PCI i8253 Baud rate clock generator Note 5a - Output to port 84h: Counter 0; Receive clock Note 6a - Output to port 85h: Counter 1; Transmit clock Note 7a - Output to port 86h: Counter 2; Clock used by different programs (time out counter) Note 8a - Output to port 87h: Mode register An example routine to initialise the 3 clocks for use of 19 200 BpS (the frequency is 1.8432*10^6/6=307,200 Hz) is shown below: def_baud EQU 6 ; 192000 bps = (1/16)*1.8432*10^6/6 ; ^ ^ ^ ^ ; | | | | ; Rate BaudFact X-Tal Def_baud timer0_ctrl EQU 00110110b timer1_ctrl EQU 01110110b timer2_ctrl EQU 10110000b ; INIT i8253 CLOCK: ld hl,def_baud ld a,timer0_ctrl ; Receive clock out (087h),a ld a,l out (084h),a ld a,h out (084h),a ; ld a,timer1_ctrl ; Transmit clock out (087h),a ld a,l out (085h),a ld a,h out (085h),a ; ld a,timer2_ctrl ; Utl clock out (087h),a ld a,l out (086h),a ld a,h out (086h),a ret Centronic Examples: This routine will do the same as the BASIC command LPRINT CHR$(A); where A is the character ASCII code. There is no check for CTRL-STOP in this routine. print: push af prtb: in a,(090h) ; Check if BUSY (0=not BUSY) rrca rrca ; Rotate bit 1 to carry jr c,prtb ; Loop if BUSY pop af ; Get back ASCII value push af out (091h),a ; Put ASCII in [a] to centronic data bus xor a out (090h),a ; Send strobe (--_--) dec a out (090h),a ; [a]=0ffh pop af ret VDP (Video Display Processor) Note 9 - Input from port 98h Read byte from VRAM. Note 10- Output to port 98h Write byte to VRAM Note 11- Input from port 99h Read the VDP status register (selected via register 0Fh on MSX2). Status register 0 (default): bit Name Expl. 0-3 5/9th Number for the 5'th sprite (9'th in screen 4-8) on a line 5 C 1 if overlapping sprites 6 5D 1 if more than 4 sprites on a horizontal line (9 in screen 4-8) 7 F Copy of the CPU interrupt (1=interrupt) Note 12- Output to port 99h Setup VRAM address for write or read, send data to register and select register Examples: This routine will do the same as the BASIC command VPOKE HL,A where HL is the VRAM address and A is the byte to write vpoke: di call setup_write_address ; Setup VRAM write start address out (098h),a ; Write byte in [a] to VRAM ret Setup_write_address: push af ; Save byte in [a] ld a,l out (099h),a ; Send LOW byteto VDP ld a,h or 01000000b ; Set bit 6 in High byte to ; indicate WRITE out (099h),a ; Send MSB to VDP pop af ret Note that once set, the VRAM WRITE address will be incremented after each byte send to the VRAM DATA WRIITE port. This routine will fill the VRAM 100h-300h with the byte 0fh fill: di ld hl,0100h ; Destination ld bc,0200h ; Number of bytes to fill ld a,0fh ; Fill byte call setup_write_address ; See routine above push af ; Save the byte fill_loop: pop af ; Get back the byte to fill out (098h),a ; Send it to VRAM push af ; Save fill byte dec bc ; Decrement counter ld a,b or c jr nz,fill_loop ; Go loop if counter <>0 pop af ; Get back fill byte ret This routine will do the same as the BASIC command A=VPEEK HL where HL is the VRAM address and A is the byte read from VRAM vpeek: di call setup_read_address ; Setup VRAM read start address in a,(098h) ; Get byte from VRAM to [a] ret Setup_read_address: ld a,l out (099h),a ; Send Low Byte to VDP ld a,h ; Note: no special bit is set to indicate READ out (099h),a ; Send High Byte to VDP ret Note that once set, the VRAM READ address will be incremented after each byte read from the VRAM DATA READ port. This routine will read the block in the VRAM addresses 100h-300h and copy it to the RAM address 9000h get_vram: di ld hl,0100h ; Source address in VRAM ld bc,0200h ; Byte counter ld de,09000h ; Destination address in RAM call read_vram ret read_vram: call Setup_read_address ; See routine above read_loop: in a,(098h) ; Read byte from VRAM address ld (de),a ; Save it to RAM inc de ; Increment RAM counter ; (VRAM counter will be incremented by ; itself) dec bc ; Decrement number of bytes to read ld a,b or c jr nz,read_loop ; Loop if not ready ret Copy the other way, i.e copy a RAM block to an address in VRAM is demonstrated by this routine, which copies the RAM addresses 9000h-9200h to the VRAM address 100h ldir_vram: di ld hl,09000h ; Source address in RAM ld bc,0200h ; Byte counter ld de,0100h ; Destination address in VRAM call read_ram ret read_ram: ex de,hl ; Swap [de] with [hl] call Setup_write_address ; See routine above ex de,hl ; Swap [de] with [hl] write_loop: ld a,(hl) ; Get byte in RAM out (098h),a ; Send it to VRAM inc hl ; Increment RAM counter ; (VRAM counter will be incremented by itself) dec bc ; Decrement number of bytes to read ld a,b or c jr nz,read_loop ; Loop if not ready ret This routine will do the same as the BASIC command VDP(B)=A where A is the byte to be send to the VDP register B write_register: out (099h),a ; Send data (note: the data is send FIRST) ld a,b ; Get the VDP register in [a] or 10000000b ; Set bit 7 to indicate register WRITE out (099h),a ; Select register ret The VDP register can be (on MSX 1) in the range of 0-7. On the MSX2 VDP (the one in the SV738 X'Press) it can be in the range of 0-47. In some of the registers, a bit will be reffered to as M1-M5. Theese bits are used to set up the VDP screen mode (BASIC screen 0-8). The relationship between the bits and the screen is: M1 M2 M3 M4 M5 Screen format 1 0 0 0 0 Text (BASIC SCREEN 0) 0 0 0 0 0 Half text (BASIC SCREEN 1) 0 0 1 0 0 Hi resolution (BASIC SCREEN 2) 0 1 0 0 0 Multicolour (BASIC SCREEN 3) 0 0 0 1 0 Scrn2 with 8 Sprites/Line (BASIC SCREEN 4) 0 0 1 1 0 256*212, 16 colours/pixel (BASIC SCREEN 5) 0 0 0 0 1 512*212, 4 colours/pixel (BASIC SCREEN 6) 0 0 1 0 1 512*212, 16 colours/pixel (BASIC SCREEN 7) 0 0 1 1 1 256*212, 256 colours/pixel (BASIC SCREEN 8) 1 0 0 1 0 80 column text screen (BASIC SCREEN0, WIDTH 80) Register 0: Mode register 0 bit Name Expl. 0 D External video input (0=input disable, 1=enable) 1 M3 Mode M3 2 M4 Mode M4 (Not on MSX 1) 3 M5 Mode M5 (Not on MSX 1) 4 IE1 Horizontal Retrace Interrupt Enable 5 IE0 Vertical Retrace Interrupt Enable 6 DG DiGitize mode 7 0 Always 0 Register 1: Mode register 1 bit Name Expl. 0 MAG Sprite zoom (0=x1, 1=x2) 1 SZ Sprite size (0=8x8, 1=16x16) 2 0 Always 0 on MSX 1 3 M2 Mode M2 4 M1 Mode M1 5 IE2 Interrupt control (50Hz (PAL), 60 Hz (NTSC) and Light pen/mouse on MVDP colour bus) (0=Disable, 1=Enable) 6 BLK Screen output control (0=Disable, 1=Enable) 7 416 VRAM size control (0=4K, 1=16K) The addresses of the VRAM has special functions. Theese can be changed via the VDP registers 2-6. VRAM addresses: The addresses for each of the 8 (MSX2) screen modes is shown below. "*" = Screen only available on MSX2 or higher. SCREEN 0 (Text mode, 40 column): Name table (char positions) 0000-03BF (See note A) Character patterns (font) 0800-0FFF (See note B) SCREEN 1 (coloured text mode, 32 column): Character patterns (font) 0000-07FF (See note B) Name table (char positions) 1800-1AFF (See note A) Sprite attribute table 1B00-1B7F (See note C) Characters colour table (8/byte)2000-201F (See note F) Sprite character patterns 3800-3FFF (See note D) SCREEN 2 (256*192 Graphics mode): Charcter patterns 0000-17FF (See note B) Name table (char positions) 1800-1AFF Sprite attribute table 1B00-1B7F (See note C) PixelByte colour table 2000-37FF (See note E) Sprite character patterns 3800-3FFF (See note D) SCREEN 3 (4x4 pixel blocks/Multicolour mode): Charcter colour patterns 0000-05FF Name table (char positions) 0800-0AFF Sprite attribute table 1B00-1B7F (See note C) Sprite character patterns 3800-3FFF (See note D) *SCREEN 4 (256*192 Graphics mode with multicolour sprites): Charcter patterns 0000-17FF (See note B) Name table (char positions) 1800-1AFF Sprite colours 1C00-1DFF Sprite attribute table 1E00-1E7F Palette 1E80-1E9F PixelByte colour table 2000-37FF Sprite character patterns 3800-3FFF *SCREEN 5 (256*212 Graphic mode, 16 colours): Matrix 0000-69FF Sprite colours 7400-75FF Sprite attribute table 7600-767F Palette 7680-769F Sprite character patterns 7800-7FFF *SCREEN 6 (512*212 Graphic mode, 4 colours): Matrix 0000-69FF Sprite colours 7400-75FF Sprite attribute table 7600-767F Palette 7680-769F Sprite character patterns 7800-7FFF *SCREEN 7 (512*212 Graphic mode, 16 colours): Matrix 0000-D3FF Sprite character patterns F000-F7FF Sprite colours F800-F9FF Sprite attribute table FA00-FA7F Palette FA80-FA9F *SCREEN 8 (256*212 Graphic mode, 256 colours): RGB Matrix 0000-D3FF (See note H) Sprite character patterns F000-F7FF Sprite colours F800-F9FF (See note I) Sprite attribute table FA00-FA7F Palette FA80-FA9F *SCREEN 0 (Text mode, 80 column): Name table (char positions) 0000-077F (086F) (See note A) Character attribute (Blink) 0800-08EF (090D) (See note G) Character patterns (font) 1000-17FF (See note B) (Addresses in pharentheses is used in 26.5 lines mode. Observe that they are overlapping). Tables explanation: Name table (Note A): Byte: Expl.: 0 Pattern number to be displayed in upper hand left corner of screen 1 Pattern number to be displayed in upper hand left corner of screen+1 2 Pattern number to be displayed in upper hand left corner of screen+2 3 Pattern number to be displayed in upper hand left corner of screen+3 ... Font (Note B): Byte (+offset): Expl.: 0-7 Pattern number 0 (First character) 0: 00000000 1: 00001000 2: 00010100 3: 00100010 = "A" 4: 00111110 5: 00100010 6: 00100010 7: 00000000 8-F Pattern number 1 (2nd character) 10-17 Pattern number 2 (3rd character) 1F-20 Pattern number 3 (4th character) ... Sprite attribute (Note C): Byte (+offset): Expl.: 0-3 Sprite 0 attribute 0: Vertical position 1: Horizontal position 2: Pattern number 3: Bit: Expl.: 0-3 Colour code 4-6 0 7 EC (Early Clock, 1=> Shift sprite 32 pixels to the left) 4-7 Sprite 1 attribute 8-B Sprite 2 attribute ... Sprite character patterns (Note D): Used like the 8*8 pixel Font in screen 0 when using 8*8 pixel sprites. When using 16*16 pixel sprites, four blocks of 8*8 pixels is organised like: Byte (+offset): Expl.: 0-7 8 Bytes, Block A 8-F 8 Bytes, Block B 10-17 8 Bytes, Block C 18-1F 8 Bytes, Block D And the sprite will be assembled on screen like this: +---------+---------+ | | | | Block A | Block C | | | | +---------+---------+ | | | | Block B | Block D | | | | +---------+---------+ PixelByte colour (Note E): Byte (+offset): Expl. 0 Colour code for 8 bits in scrn pos X=0-7, Y=0 Bit: Expl.: 0-3 Colour for bit reset ("0") in pattern table 4-7 Colour for bit set ("1") in pattern table 1 Colour code for 8 bits in scrn pos X=0-7, Y=1 2 Colour code for 8 bits in scrn pos X=0-7, Y=2 ... 8 Colour code for 8 bits in scrn pos X=8-15, Y=0 9 Colour code for 8 bits in scrn pos X=8-15, Y=1 A Colour code for 8 bits in scrn pos X=8-15, Y=2 ... Characters colour table (Note F): Byte (+offset): Expl. 0 Colour code for patterns 0-7 in pattern table Bit: Expl.: 0-3 Colour for bit reset ("0") in pattern table 4-7 Colour for bit set ("1") in pattern table 1 Colour code for patterns 8-F in pattern table 2 Colour code for patterns 10-17 in pattern table Characters attribute (Note G): Byte (+offset): Expl. 0 Attribute bits for character patterns 0-7 Bit: Expl.: 7 Char 0, "1" = Blink mode on, "0" = Blink mode off 6 Char 1, "1" = Blink mode on, "0" = Blink mode off 5 Char 2, "1" = Blink mode on, "0" = Blink mode off 4 Char 3, "1" = Blink mode on, "0" = Blink mode off ... 1 Attribute bits for character patterns 8-F 2 Attribute bits for character patterns 10-17 ... RGB Matrix (Note H): Byte (+offset): Expl. 0 Red, Green and blue combination for first pixel Bit: Expl.: 0-1 Blue, 0-3 2-4 Red, 0-7 5-7 Green, 0-7 1 Red, Green and blue combination for 2nd pixel 2 Red, Green and blue combination for 3rd pixel ... (4(Blue)*8(Red)*8(Green)=256 colours totally) Sprite colours (Note I): Byte (+offset): Expl.: 0-7 Colour map for sprite 0 Upper left part (Horizontal lines) 0: Colour for line 0: Bit: Expl.: 0 Blue on/off (1=on, 0=off) 1 Red on/off (1=on, 0=off) 2 Green on/off (1=on, 0=off) 3 Intensity (1=Light, 0=dark) 4-7 Not used 1-7: Colour for line 1-7 8-F Colour map for sprite 0 Upper right part (if using 16*16pixel sprites). 10-17 Colour map for sprite 1 Upper left part ... The base registers are the registers 2-6. For further information (about how the registers are handled to form a 16-bit address), see the MSX RED BOOK by Kuma. Register 2: Name table base address Bit 7 6 5 4 3 2 1 0 Name 0 A16 A15 A14 A13 A12 A11 A10 Register 3: colour table base address Low Bit 7 6 5 4 3 2 1 0 Name A13 A12 A11 A10 A09 A08 A07 A06 Register 4: Pattern generator base address Bit 7 6 5 4 3 2 1 0 Name 0 0 A16 A15 A14 A13 A12 A11 Register 5: Sprite attribute table base address Low Bit 7 6 5 4 3 2 1 0 Name A14 A13 A12 A11 A10 A09 A08 A07 Register 6: Sprite pattern generator base address Bit 7 6 5 4 3 2 1 0 Name 0 0 A16 A15 A14 A13 A12 A11 Register 7: colour register. bit Name Expl. 0-3 TC0-3 Background colour in SCREEN 0 (also border colour in SCREEN 1-3) 4-7 BD0-3 Foreground colour in SCREEN 0 The bits 0-3 and 4-7 can hold a number in the range of 0-15. The corresponding colours are: 0 = Transparent 8 = Medium red 1 = Black 9 = Light red 2 = Medium green 10= Dark yellow 3 = Light green 11= Light yellow 4 = Dark blue 12= Dark green 5 = Light blue 13= Magenta 6 = Dark red 14= Gray 7 = Cyan 15= White *** MSX1 VDP REGISTERS ENDS HERE! *** Register 8: Mode register 2 bit Name Expl. 0 BW 32 Greylevel MVDPmode out trough CompositeVideo output. (Normally composite video and RGB are not generated from this output but from another on the MVDP). 1 SP ? Sprite (0=On, 1=Off) 2 VR0 VRAM size and speed 3 VR1 VRAM size and speed 4 CB colour Bus direction (0=Output, 1=Input) 5 TP ?Transparent from palette 6 LCS Lightpen Select (active 1) connected trough colourbus 7 MSE Mouse select (active 1) connected trough colourbus Register 9: Mode register 3 bit Name Expl. 0 DC DLCLK Dot Clock Direction (0=Dot clock Input, 1=Output) 1 NT NTSC (0=60Hz, 1=50Hz) 2 E0 Even Odd (0=Normal, 1=Two screen) 3 IL Interlace (1=On, 0=Off) 4 S0 Simultaneus mode 5 S1 Simultaneus mode 6 0 Always 0 7 LN Vertical higth (pixels) (0=192, 1=212) Simultaneus mode: S0 S1 Expl. 0 0 Normal (Intern) 0 1 Mix 1 x External(Digitize) Register 0Ah: colour table base address High Bit 7 6 5 4 3 2 1 0 Name 0 0 0 0 0 A16 A15 A14 Register 0Bh: Sprite attribute base address High Bit 7 6 5 4 3 2 1 0 Name 0 0 0 0 0 0 A16 A15 Register 0Ch Inverse text colour bit Name Expl. 0-3 BC0-3 Inverse/blink text background colour 4-7 T20-3 Inverse/Blink text forground colour The bits 0-3 and 4-7 can hold a number in the range of 0-15. The corresponding colours are the same as for register 7. Register 0Dh: Blinking period bit Name Expl. 0-3 OF0-3 Off blink time (1/5 sec) 4-7 ON0-3 On blink time (1/5 sec) Register 0Eh: VRAM access (VRAM address select, higher address lines) Bit Name Expl. 0 A14 1 if 4000h and forward 1 A15 1 if 8000h and forward 2 A16 1 if 10 000h and forward 7-3 0 Always 0 A16 A15 A14 Expl. 0 0 0 0 - 3FFFh (VRAM memory) 0 0 1 4000h - 7FFFh 0 1 0 8000h - BFFFh 0 1 1 C000h - FFFFh 1 0 0 10000h -13FFFh 1 0 1 14000h -17FFFh 1 1 0 18000h -1BFFFh 1 1 1 1C000h -1FFFFh To setup a VRAM address (see note about the BASIC command VPOKE) the first byte send to the VDP is the low byte. Then the second byte, containing the high byte, is send with bit 6 set to 1. So to setup VRAM address 19F18h for write, the first operation to be done is to setup the higher address lines: ld a,00000110b ; 18000h - out (099h),a ; Send data ld a,0Eh ; Select VDP register 0Eh or 10000000b ; Bit 7=1 indicates REGISTER out (099h),a Then the low address (0-3FFFh) has to be send to the VDP. Here we send the word 1F18h: ld a,18h ; Low byte out (099h),a ld a,1Fh ; High byte or 01000000b ; Bit 6=1 indicates ADDRESS out (099h),a The byte can then be written to port 098h: ld a,0Fh ; Byte to write out (098h),a The instructions above does the same thing as the BASIC command VPOKE &h19F18,&h0F Register 0Fh: Status register bit Name Expl. 0-3 S0-3 Status register number (0-9) 4-7 0 Always 0 b6 Shake Register 010h: Palette # bit Name Expl. 0-3 C0-3 colour palette register number (0-15 for colour 0-15) to receive data from port 09Ah 4-7 0 Always 0 Register 011h: Register pointer bit Name Expl. 0-5 R0-5 VDP register number 6 0 Always 0 7 AII Auto increment RP (Register Pointer) (0=on, 1=off) Register 012h: Display adjust bit Name Expl. 0-3 H0-3 Horizontal adjust (0-0Fh, +-8 pixels) 4-7 V0-3 Vertical adjust (0-0Fh, +-8 pixels) Register 013h: Interrupt line bit Name Expl. 0-7 IL0-7 Interrupt line Register 014h: colour burst register 1 bit Name 0-7 0 Register 015h: colour burst register 2 Bit 7 6 5 4 3 2 1 0 Name 0 0 1 1 1 1 0 1 Register 016h: colour burst register 3 Bit 7 6 5 4 3 2 1 0 Name 0 0 0 1 0 1 0 1 Register 017h: Display offset bit Name Expl. 0-7 DO0-7 Display offset Y (0-255). - - - - Register 020h: Register 021h: Source X Low byte Source X High byte Register 022h: Register 023h: Source Y Low byte Source Y High byte Register 024h: Register 025h: Destination X Low byte Destination X High byte Register 026h: Register 027h: Destination Y Low byte Destination Y High byte Register 028h: Register 029h: Number of X dots low byte Number of X dots high byte Register 02Ah: Register 02Bh: Number of Y dots low byte Number of Y dots high byte Register 02Ch: colour register bit Name Expl. 0-3 CL0-3 ? Graphic command colour register (LINE, POINT...) 4-7 CH0-3 ? Graphic command colour register (LINE, POINT...) Register 2D: Argument register bit Name Expl. 0 MAJ Longest side, used by line 0=X, 1=Y 1 EQ ?Search? 2 DIX X step direction (0=right, 1=left) 3 DIY Y step direction (0=down, 1=up) 4 MXS Source external memory (0=128K VRAM, 1=64K VRAM) 5 MXD Destination external memory (0=128K VRAM, 1=64K extra) 6 MXC CPU Access external memory? (0=128K VRAM, 1=64K VRAM) 7 0 Always 0 Register 2E: Command register bit Name Expl. 0-2 AR0-2 Logical argument, see below. 3 TRN Transparet no effect 4-7 C0-3 Command, see below. Commands (C0-3): Value: Expl.: 0 Stop 4 Point, VRAM -> VDP 5 Pset, VDP -> VRAM 6 Search, VRAM -> VRAM 7 Line, VDP -> VRAM 8 Logical move, VDP -> VRAM 9 Logical move, VRAM -> VRAM A Logical move, VRAM -> CPU B Logical move, CPU -> VRAM C High speed move (bits 0-3 has no effect), VDP -> VRAM D High speed move (bits 0-3 has no effect), VRAM -> VRAM E High speed move (bits 0-3 has no effect), VRAM -> CPU F High speed move (bits 0-3 has no effect), CPU -> VRAM Arguments (AR0-AR2): Value: Name: Expl.: 0 PSET Set bits, set old bits to 0 1 AND Mask bits 2 OR Set bits, include old 3 XOR Swap new bits 4 NOT Set new bits to 0 Note 12(b)- Output to port 9Ah This is the colour palette data port. The data is send consists of two bytes: Byte 1: Byte 2: Bit: Expl.: Bit: Expl.: 0-2 = Blue data (0-7) 0-2 = Green data (0-7) 3 = Always 0 (no effect) 3-7 = Always 0 (no effect) 4-6 = Red data (0-7) 7 = Always 0 (no effect) Examples: This routine will define the colour white (15 in BASIC) to the new values RED=7, GREEN=4 and BLUE=1 (light red). First the colour number to change must be defined by sending colour number (0-15) to VDP register 10h. Then the Red, Green and Blue colours are sent trough port 09Ah. This mix of R, G and B will give colour # 15 a colour of lighgt red. RED EQU 7 ; 0-7 GREEN EQU 4 ; 0-7 BLUE EQU 1 ; 0-7 di ld a,0fh ; colour to change=colour 15(orginally white) out (099h),a ; Send data ld a,090h ; =Register 10h with bit 7 set nop nop out (099h),a ; Select register ; ld a,RED*16+BLUE ; Setup red and blue in reg. [a] out (09ah),a ; Send red & blue ld a,GREEN ; Setup green out (09ah),a ; Send it. ret To set a colour to pure red, the other bits for green and blue should be set to 0. PSG (Programmable Sound Generator) Note 13- Port A0h WRITE = PSG register select. This port selects the current PSG register (0-15). Registers are: 0 = Fine freq. channel A (0-255) 1 = Freq. channel A (0-15) 2 = Fine freq. channel B (0-255) 3 = Freq. channel B (0-15) 4 = Fine freq. channel C (0-255) 5 = Freq. channel C (0-15) 6 = Noise period (0-31) 7 = Mixer bit Expl. 0 = Channel A tone enable (0=Enable,1=Disable) 1 = Channel B tone enable (0=Enable,1=Disable) 2 = Channel C tone enable (0=Enable,1=Disable) 3 = Channel A noise enable (0=Enable,1=Disable) 4 = Channel B noise enable (0=Enable,1=Disable) 5 = Channel C noise enable (0=Enable,1=Disable) 6 = I/O port A mode (0=input, 1=Output) 7 = I/O port B mode (0=input, 1=Output) 8 = Volume channel A (0-15, 16=Envelope) 9 = Volume channel B (0-15, 16=Envelope) 10= Volume channel C (0-15, 16=Envelope) 11= Envelope fine freq. (0-255) 12= Envelope freq. (0-255) 13= Envelope shape (0-15) Output frequency (tone): f = 3.579M/2 T ------------------- 16*(256*fine+coarse) Where "coarse" are one of the coarse frequency setting registers, 1,3 or 5 and "fine" are one of the fine frequency setting registers, 1,2 or 4. Output frequency (noise): f = 3.579M/2 N -------------- 16*NoisePeriod Where "NoisePeriod" are register 6. Envelope frequency (tone or noise): f = 3.579M/2 E ---------------------- 256*(256*ECoarse+EFine) Where "ECoarse" are the coarse envelope frequency setting register 12 and "EFine" are the fine envelope frequency setting register 11. Note that the envelope period is 1 ----- f E C A A H O T L L N T T D T 0 0 X X \________ 0 0 1 X X /________ 4 1 0 0 0 \\\\\\\\\ 8 (Repeating, see figure) 1 0 0 1 \________ 9 1 0 1 0 \/\/\/\/\ 10 (Repeating, see figure) 1 0 1 1 \ 11 (See figure) 1 1 0 0 ///////// 12 (Repeating) 1 1 0 1 / 13 1 1 1 0 /\/\/\/\/\ 14 (Repeating) 1 1 1 1 / 15 14= I/O port A (Joystick and cassette) bit Expl. 0 = Joystick UP (0=Moved, 1=Not moved) 1 = Joystick DOWN (0=Moved, 1=Not moved) 2 = Joystick LEFT (0=Moved, 1=Not moved) 3 = Joystick RIGHT (0=Moved, 1=Not moved) 4 = Joystick trigger A 5 = Joystick trigger B 6 = Keyboard mode (On japanese machines only) 7 = Cassette input 15= I/O port B (Joystick select) bit Expl. 0 = 1 (Used as handshaking output if touchpad) 1 = 1 (Used as handshaking output if touchpad) 2 = 1 (Used as handshaking output if touchpad) 3 = 1 (Used as handshaking output if touchpad) 4 = Pulse 1 (Positive pulse starting a monostable timer) 5 = Pulse 2 (Positive pulse starting a monostable timer) 6 = Joystick select (0=Connector 1, 1=Connector 2) 7 = Kana LED (Keyboard mode indicator. On japanese machines only) Bits 4 and 5 is used by a program wich uses a paddle. A short positive edge pulse on bit 4 (or 5) starts a monostable timer (in the attatched paddle) and the paddle sets one of the joystick bits in register 14 low (FIRE A (FIRE B),L,R,D or U). When the monostable times out, the joystick bit in port 14 is set high again. The length of the counting period of the monostable timer is set (in the attatched paddle) by a variable resistor. The computer determine the position of the variable resistor by measuring the time while the joystick bit in register 14 is low. PULSE _________|-|______________________ FIRE A/B or ---------|______________|--------- L R D U | - - - - - - -| = Variable resistor Note 14- Port A1h WRITE = PSG data write. Used to send data to current PSG register. Note 15- Port A2h READ = PSG data read. Used to read data from current PSG register. Examples: This routine will do the same as the BASIC command SOUND A,B where A is the PSG register and B is the byte to write sound: out (0A0h),a ; Select register ld a,b out (0A1h),a ; Send data ret How to read a byte from a register is shown in this routine (Input: [a]=PSG register, Output: [a]=Data read) read_psg: out (0A0h),a ; Select register in a,(0A2h) ; Read data ret This rotine will read joystick 1 or 2: F3 di 3E 0F ld a,0fh Write this for Write this for D3 A0 out (0a0h),a Joystick port 1: Joystick port 2: DB A2 in a,(0a2h) E6 DF / E6 AF and 11011111b; 0DFh and 10101111b; 0AFh F6 4C / F6 03 or 01001100b; 04Ch or 00000011b; 003h D3 A1 out (0a1h),a 3E 0E ld a,0eh D3 A0 out (0a0h),a DB A2 in a,(0a2h) Now register [a] will have the following configuration for joystick in port 1 (or port 2): Bit #: 76 5 4 3210 || | | |||| Name: 10 TRG2 TRG1 RLDU Where TRG2 is the second trigger button (not used on most Commodore joysticks). PPI (Programmable Peripheral Interface) Note 16 - Port 0A8h READ = PPI port A (Primary slot register read) Reads the current PSLOT (Primary Slot) configuration. Returned byte is: bit Expl. 0-1 = Primary slot number (0-3) for memory page 0 (Addr. 0000-3FFF) 2-3 = Primary slot number (0-3) for memory page 1 (Addr. 4000-7FFF) 4-5 = Primary slot number (0-3) for memory page 2 (Addr. 8000-BFFF) 6-7 = Primary slot number (0-3) for memory page 3 (Addr. C000-FFFF) Note 17 - Port 0A8h WRITE = PPI port A (Primary slot register setup) Selects the current PSLOT (Primary Slot) configuration. Byte to write is: bit Expl. 0-1 = Primary slot number (0-3) for memory page 0 (Addr. 0000-3FFF) 2-3 = Primary slot number (0-3) for memory page 1 (Addr. 4000-7FFF) 4-5 = Primary slot number (0-3) for memory page 2 (Addr. 8000-BFFF) 6-7 = Primary slot number (0-3) for memory page 3 (Addr. C000-FFFF) The standard RAM/ROM areas on a MSX machine is described by the map below: (Note: the characters "a-i" is special memory blocks, see notes). STANDARD |STANDARD |CARTRIDGE|SYSTEM ROM |RAM |MEMORY |MEMORY -----------------|---------|---------|--------- PSLOT#: : 0 : : 1 : : 2 : : 3 | --------|SSLOT#:| |SSLOT#:| |SSLOT#:| |SSLOT#:| |0|1|2|3| |0|1|2|3| |0|1|2|3| |0|1|2|3| Addresses: PAGE: --- - - - -=- - - - -=- - - - -=- - - - - | | | | |=| | | | |=| | | | |=| | | | | 0 0 |a| | | |=|c| | | |=| | | | |=| |h| | | | | | | |=| | | | |=| | | | |=| | | | | | | | | |=| | | | |=| | | | |=| | | | | 3FFF --- - - - -=- - - - -=- - - - -=- - - - -- | | | | |=| | | | |=| | | | |=| | | | | 4000 1 |b| | | |=|d| | | |=| | | | |=|g|i| | | | | | | |=| | | | |=| | | | |=| | | | | | | | | |=| | | | |=| | | | |=| | | | | 7FFF --- - - - --- - - - -=- - - - -=- - - - -- | | | | |=| | | | |=| | | | |=| | | | | 8000 2 | | | | |=|e| | | |=| | | | |=| | | | | | | | | |=| | | | |=| | | | |=| | | | | | | | | |=| | | | |=| | | | |=| | | | | BFFF --- - - - --- - - - -=- - - - -=- - - - -- | | | | |=| | | | |=| | | | |=| | | | | C000 3 | | | | |=|f| | | |=| | | | |=| | | | | | | | | |=| | | | |=| | | | |=| | | | | | | | | |=| | | | |=| | | | |=| | | | | FFFF ------------------------------------------ Notes: (Memory configuration on a MSX2 expanded SV738 X'Press, memory mapper for 256 Kbyte not implemented) a= ROM BIOS (Games often use this ROM block) b= ROM BASIC (This is the BASIC interpreter) c= RAM 16K (1/4 of 64K bytes standard RAM) \ d= RAM 16K (1/4 of 64K bytes standard RAM) | e= RAM 16K (1/4 of 64K bytes standard RAM) | = 64K bytes totally f= RAM 16K (1/4 of 64K bytes standard RAM) / g= ROM RS232 (Port drivers & terminal program) h= ROM MSX2 (Complement to BASIC ROM) i= ROM DOS (FDC drivers & MSX DOS) *** OBSERVE *** The memory location 7FBC-7FBF in [PSLOT 3, SSLOT 1] are used as command port for the FDC (Floppy Disk Controller) chip, FD1793. Writing to this area might destroy the inserted disk. Memory locations in that area: reqpt equ 07fbch ; Data request port read only ; bit 7=1 for 1793 interrupt ; bit 6=0 for 1793 data request selpt equ 07fbch ; Drive select port ; (write 0 to turn off drive motor) ; bit 0=1 for select drive 0 ; bit 1=1 for select drive 1 ; bit 2=1 for select side 1 ; bit 3=1 for motor on compt equ 07fb8h ; command port write only sttpt equ 07fb8h ; Status port read only trkpt equ 07fb9h ; Track register port (R/W) secpt equ 07fbah ; Sector register port (R/W) datapt equ 07fbbh ; data register port (R/W) For further information about the FD1793 commands, see data manual. Note 18 - Port 0A9h READ = PPI port B (Keyboard columns): Reading this port will get back the state of the selected keyboard line (selected via port 0AAh). Each bit corresponds to one of 8 keys on each line. bit Name Expl. 0-7 KC0-7 Keyboard line status The matrix connected keyboard can be described by this map: Bit#:| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | | | | | | | | | Line: | | | | | | | | | ---------+-----+-----+-----+-----+-----+-----+-----+-----| 0 | "7" | "6" | "5" | "4" | "3" | "2" | "1" | "0" | ---------+-----+-----+-----+-----+-----+-----+-----+-----| 1 | ";" | "]" | "[" | "\" | "=" | "-" | "9" | "8" | ---------+-----+-----+-----+-----+-----+-----+-----+-----| 2 | "B" | "A" | "£" | "/" | "." | "," | "'" | "`" | ---------+-----+-----+-----+-----+-----+-----+-----+-----| 3 | "J" | "I" | "H" | "G" | "F" | "E" | "D" | "C" | ---------+-----+-----+-----+-----+-----+-----+-----+-----| 4 | "R" | "Q" | "P" | "O" | "N" | "M" | "L" | "K" | ---------+-----+-----+-----+-----+-----+-----+-----+-----| 5 | "Z" | "Y" | "X" | "W" | "V" | "U" | "T" | "S" | ---------+-----+-----+-----+-----+-----+-----+-----+-----| 6 | F3 | F2 | F1 |CODE | CAP |GRAPH|CTRL |SHIFT| ---------+-----+-----+-----+-----+-----+-----+-----+-----| 7 | RET | SEL | <== |STOP | TAB | ESC | F5 | F4 | ---------+-----+-----+-----+-----+-----+-----+-----+-----| 8 |RIGHT|DOWN | UP |LEFT | DEL | INS |HOME |SPACE| ---------------------------------------------------------- Note 18(b) - Port 0A9h WRITE= PPI port B (Keyboard columns): ? Writing to this port is not allowed (?). Note 19 - Port 0AAh READ = PPI port C (Keyboard line and Cassette): bit Name Expl. 0-3 KB0-3 Keyboard line (0-8 on SV738 X'Press) 4 CASON Cassette motor relay (0=On, 1=Off) 5 CASW Cassette audio out (Pulse) 6 CAPS CAPS-LOCK lamp (0=On, 1=Off) 7 SOUND Keyboard klick bit (Pulse) Note 19(b) - Port 0AAh WRITE = PPI port C (Keyboard and Cassette control): bit Name Expl. 0-3 KB0-3 Keyboard line select (0-8 on SV738 X'Press) 4 CASON Cassette motor relay control (0=On, 1=Off) 5 CASW Cassette audio out (Pulse) 6 CAPS CAPS-LOCK lamp control (0=On, 1=Off) 7 SOUND Keyboard klick bit (Pulse) Examples: This routine will detect if a key is pressed: DB AA in a,(0AAh) ; Get old value for port C. E6 F0 and 0f0h ; Don't change bit 4-7 F6 __ or LINE ; Set the keyboard line (0-8). D3 AA out (0AAh),a ; Send it to port C (KB0-3). DB A9 in a,(0A9h) ; Read the line's columns (port B) E6 __ and bbbbbbbb ; Mask the keys we don't want 20 __ jr z,pressed ; Jump if depressed. This routine will produce a tone from the keyclick bit: loop: DB AA in a,(0AAh) ; Get old value for port C. EE 80 xor 080h ; Swap bit 7 D3 AA out (0AAh),a ; Send it to port C. 00 nop ; Changing the delay here will 00 nop ; change the frequency. 18 F6 jr loop ; Go back to the loop. Note 20 - Port 0ABh WRITE = PPI mode or reset/set bit port This port is used in two ways depending on bit 7. If bit 7 is set to 1, this port will be used as a mode setup port. If bit7=0 this port will be used to set or reset a bit in port C. PPI mode port (bits): | --- GROUP A --- | --- GROUP B --- 7 | 6 5 4 3 | 2 1 0 | | | | | | | | | | 1 | A&C A C Upper | B&C B C Lower | MODE Dir Dir 1=Input | Mode Dir 1=Input Dir 1=Input | 00=Mode 0 1=Input 0=Output | 0=Mode 0 0=Output 0=Output | 01 Mode 1 0=Output | 1=Mode 1 | 1x Mode 2 | Mode 0: Basic input/output (Mode setup by reset) Mode 1: Strobed input/output Mode 2: Bi-Directional bus In other words: Bit Name Expl. 0 CLOWER Port C (lower four bits) direction (0=Output (MSX), 1=Input) 1 BDIR Port B direcition (0=Output, 1=Input (MSX)) 2 B&C Port B and lower four bits of port C operating mode. (0=Normal (MSX), 1=Strobed) 3 CUPPER Port C (Upper four bits) direction (0=Output (MSX), 1=Input) 4 ADIR Port A direction (0=Output (MSX), 1=Input) 5-6 A&C Port A and upper four bits of port C operating mode. (00=Normal mode (MSX), 01=Strobed mode, 1x=Bidirectional mode (x=Don't care)). 7 - 1 if mode setup function is selected. The mode port can be used to directly set or reset any bit of port C when bit 7 is 0. Bit Name Expl. 0 - Set/reset the bit (0=Reset, 1=Set) 1-3 - Bit number (0-7) 4-6 - Not used 7 - 0 if set/reset function selected. Note 20(b) - Port 0BAh READ = PPI mode or reset/set bit port ? Reading from this port is not allowed (?). RTC - Real Time Clock Note 21(a)- Port 0B4h = RTC Register select port (write only) Bit Name Expl. 0-3 ? RTC register (0-15) 4-7 ? Not used (don't care) Note 21(b)- Port 0B5h = RTC data read/write port Bit Name Expl. 0-3 ? RTC data read/write 4-7 ? Not used (set to 1) RAM Note 22- Ports 0FCh-0FFh. These ports are normally not connected on a standard MSX1 SV738 X'press. However, upgrading to MSX 2 is usually done by changing some ROM's, set the VRAM to 128Kb and set the internal RAM to 256Kb. The last thing is done by mapping 16Kbyte blocks to the ports 0FCh-0FFh. The normal format of theese ports are: 0FCh=03 RAM block # for memory page 0 (Addr. 0000-3FFF) 0FDh=02 RAM block # for memory page 1 (Addr. 4000-7FFF) 0FEh=01 RAM block # for memory page 2 (Addr. 8000-BFFF) 0FFh=00 RAM block # for memory page 3 (Addr. C000-FFFF) The number in each port is the number of the current 16Kbyte RAM block (0-255). Observe that more than one memory page can use the same 16Kbyte block. The total RAM (fully expanded) is (16Kbyte * 256 blocks)= 4Mbyte. Usually the ports 0FCh-0FFh only uses 4 bits, so the maximum RAM is then (16Kbyte * 16 blocks)= 256Kbyte. Page: Port: Addr.: Available RAM blocks: --------- 0000h --------- --------- | 16Kb | | 16Kb | | 16Kb | 0 0FCh | BLOCK | | BLOCK | | BLOCK | | #3 | | #4 | | #5 | --------- 3FFFh --------- --------- --------- 4000h --------- --------- | 16Kb | | 16Kb | | 16Kb | 1 0FDh | BLOCK | | BLOCK | | BLOCK | | #2 | | #6 | | #7 | --------- 7FFFh --------- --------- --------- 8000h --------- --------- | 16Kb | | 16Kb | | 16Kb | 2 0FEh | BLOCK | | BLOCK | | BLOCK | | #1 | | #8 | | #9 | --------- BFFFh --------- --------- --------- C000h --------- --------- | 16Kb | | 16Kb | | 16Kb | 3 0FFh | BLOCK | | BLOCK | | BLOCK | | #0 | | #10 | | #11 | --------- FFFFh --------- --------- ... and so on to --------- --------- | 16Kb | | 16Kb | | BLOCK | | BLOCK | | #254 | | #255 | --------- --------- HARDWARE PORTS Front view 9-PIN D-SUB AMP 9 9-PIN D-SUB AMP 9 (FEMALE) (MALE) 5 4 3 2 1 1 2 3 4 5 ------------- ------------- \ o o o o o / \ * * * * * / \ o o o o / \ * * * * / ------- ------- 9 8 7 6 6 7 8 9 DE-09x-P-F DE-09x-P-M 25-PIN D-SUB (FEMALE) 13 12 11 10 9 8 7 6 5 4 3 2 1 --------------------------- \ o o o o o o o o o o o o / \ o o o o o o o o o o o / --------------------- 25 24 23 22 21 20 19 18 17 16 15 14 DE-25x-P-F 25-PIN D-SUB (MALE) 1 2 3 4 5 6 7 8 9 10 11 12 13 --------------------------- \ * * * * * * * * * * * * / \ * * * * * * * * * * * / --------------------- 14 15 16 17 18 19 20 21 22 23 24 25 DE-25x-P-M Micro-Ribbon / 14-pin AMPhenol Micro-Ribbon / 14-pin AMPhenol (FEMALE) (MALE) 7 6 5 4 3 2 1 1 2 3 4 5 6 7 ------------------- ------------------- | H H H H H H H | | _ _ _ _ _ _ _ | \ =============== / \ =============== / \ H H H H H H H / \ - - - - - - - / --------------- --------------- 14 13 12 11 10 9 8 14 13 12 11 10 9 8 57LE-40140 57-30140 Phono RCA Phono RCA (FEMALE) (MALE) --- --- ( O ) ( * ) --- --- 1 2 1 2 PRC/1CS SPC/10 2.54 space DGE (FEMALE) Polarisation mark |___| 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 +---------------------------------------------------+ | H H H H H H H H H H H H H H H H H H H H H H H H H | | ================================================= | | H H H H H H H H H H H H H H H H H H H H H H H H H | +---------------------------------------------------+ 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 DGE DIN audio (FEMALE) 2 _____ / o \ 4 / o o \ 5 3 ( o o o ) 1 (8=center pin) 7 \ o o / 6 \__^__/ 9 DIN-45326 INTERNAL (or external) 3.5" drive (MALE) rear, *=pin F-353 CHINON _____________________________________________________ PC __ 1-----------------------------------+ ---------- | * * * * * * * * * * * * * * * * * | * * * * | * * * * * * * * * * * * * * * * * | +-----------------------------------+ | | | | +5V | GND | GND +12V Power supply 34-pin 2.54 contact Pin number: 1 3 5 7 9 (upper line) * * * * * ..... etc... * * * * 2 4 6 8 (lower line) EXTERNAL 5 1/4" DRIVE (MALE) 2 4 6 8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ (PC board) - - - - - - - - - - - - - - - - - 1 3 5 7 9 .... ^ | (Polarisation mark) Note: Setting the drive signal connector upside-down will cause the drive LED lamp to light continously and the drive will not work. Mostly, this will not damadge the system. 5 1/4" drive Power supply (MALE ON DRIVE) +12V GND GND +5V | | | | ----------------------- | * * * * | \_____________________/ U WARNING! PIN CONFIGURATION FOR CONNECTOR ON DISK DRIVE! CHANGING +12V AND +5V MIGHT DESTROY TTL LEVEL IC'S IN THE DISK DRIVE. PIN CONFIGURATION OC= Open collector -= No specified direction I= Input (to MSX) NC= Not connected O= Output (to device) RS-232-C Serial DE-09x-P-F Pin Name EIA RS232 I/O Comment :CCITT V24 1 PG AA:101 - Protective Ground 2 TD BA:103 O Transmitted Data 3 RD BB:104 I Received Data 4 RTS CA:105 O Request To Send 5 CTS CB:106 I Clear To Send 6 DSR CC:107 I Data Set Ready 7 SG AB:102 - Signal Ground 8 DCD CF:109 I Data Channel received line signal Detector, Data Carrier Detect 9 DTR 108/2 O Data Terminal Ready Centronic Paralell 57LE-40140 1 _STB O Centronic Strobe pulse (char data on PDB lines) 2 PDB0 O Character data line 3 PDB1 O 4 PDB2 O 5 PDB3 O 6 PDB4 O 7 PDB5 O 8 PDB6 O 9 PDB7 O 10 N.C - 11 BUSY I Signals if printer is busy 12 N.C - 13 N.C - 14 GND - Signal ground Shugart 3.5" or 5 1/4" DE-25x-P-F Disk drive (external) 1 +12V O 2 +5V O 3 +5V O 4 _INDEX I This interface signal is provided by the drive each time an index or sector hole is sensed by the INDEX/SECTOR sensing photo transducer. Low when passing index hole or no disk inserted. 5 _DRIVE SELECT 1 O Will turn drive 1 on. Drive number is set via the shunts in each drive. 6 DIRECTION O Selects direction of the R/W head for the STEP signal. "1"=Out (away from center), "0"=In, (towards the center of the disk). 7 _STEP O Moves the R/W head in the direction set by DIRECTION pin. 8 WRITE DATA O Bit stream of data to write on disk. Should be "0" when reading data. 9 _WRITE GATE O When"0":Enables WRITE DATA to be written on the diskette. When"1":Enables STEP and disables WRITE DATA. 10 _TRACK 00 I "0" when R/W head is over the track number 0 (the outermost data track). 11 _WRITE PROTECT I When "0": No data can be written on the disk. 12 READ DATA I Data read from the diskette. Normally kept high. 13 _SIDE SELECT O Selects one of the two sides on a diskette. "1"= Side 0 "0"= Side 1 14 +12V O 15 +12V O 16 +5V O 17 _DRIVE SELECT 0 O Will turn drive 0 on. Drive number is set via the shunts in each drive. 18 _MOTOR ON O Low level turns the selected drive motor(s) on. 19 READY I "0" when drive has counted two index pulses after drive motor gives normal speed. "1" when drive is not ready. 20,21,22 GND - Logical ground. 23,24,25 GND - Shugart 3.5" 34-pin 2.54 contact (3.5") Disk drive or PC-board (5 1/4") (internal) or 5 1/4" 2 DISK CHANGE I 4 _IN USE O 6 _DRIVE SELECT 3 O 8 _INDEX I 10 _DRIVE SELECT 0 O 12 _DRIVE SELECT 1 O 14 _DRIVE SELECT 2 O 16 _MOTOR ON O 18 DIRECTION O 20 _STEP O 22 WRITE DATA O 24 _WRITE GATE O 26 _TRACK 00 I 28 _WRITE PROTECT I 30 READ DATA I 32 _SIDE SELECT O 34 _READY I 1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31,33 GND Joystick MSX std DE-09x-P-M 1 FWD I Joystick pushed forward when high 2 BACK I Backward 3 LEFT I Left 4 RIGHT I Right 5 +5V O 50mA power supply 6 TRG1 I/O Trigger A / output 1 7 TRG2 I/O Trigger B / Output 2 8 OUTPUT O Output 3 9 GND - Signal ground Casette MSX std DIN-45326 1 GND - Signal ground 2 GND - 3 GND - 4 CMTOUT O Sound output 5 CMTIN I Sound input 6 REM+ O Remote control (from relay) 7 REM- O Remote control (from relay) 8 GND - Signal ground 9 GND - Frame ground Video Composite PRC/1CS 1 Monitor video O 2 Ground - Audio (mono) 200mV PRC/1CS 1 Mono, mixed SOUNDIN, O PPI and PSG 2 Ground - RF video Antenna PRC/1CS 1 Composite RF signal O for TV 2 Ground - Expansion MSX std DGE 1 _CS1 O Memory read in addresses 4000-7FFF 2 _CS2 O Memory read in addresses 8000-BFFF 3 _CS12 O Memory read in addresses 4000-BFFF 4 _SLTSL O Low when SLOT 2 (cartridge slot) is selected 5 reserved - NC, Reserved for future expansion. Do not use. 6 _RFSH O Refresh signal from CPU 7 _WAIT I OC, Tells CPU to wait. Refresh signal is not maintained. 8 _INT I OC, Requests a interrupt to CPU (call to addr. 38h). 9 _M1 O CPU fetches first part of instruction from memory 10 _BUSDIR I NC, was used to control the direction of external data bus buffer. It is on LOW level when data is sent by the cartridge. 11 _IORQ O I/O (port) request signal. (address bus holds valid port address). 12 _MREQ O Memory request signal. (address bus holds valid memory address). 13 _WR O Write signal from CPU (used as strobe to device) 14 _RD O Read signal from CPU (used as strobe to device) 15 _RESET I System reset signal. [PC]=0, [I]=0,[R]=0. 16 Reserved - NC, Reserved for future expansion. Do not use. 17 A0 O Address bus. 18 A1 O 19 A2 O 20 A3 O 21 A4 O 22 A5 O 23 A6 O 24 A7 O 25 A8 O 26 A9 O 27 A10 O 28 A11 O 29 A12 O 30 A13 O 31 A14 O 32 A15 O 33 D0 I/O Data bus. 34 D1 I/O 35 D2 I/O 36 D3 I/O 37 D4 I/O 38 D5 I/O 39 D6 I/O 40 D7 I/O 41 GND - Signal/power ground 42 CLOCK O CPU clock, 3.579 M Hz. 43 GND - Signal/power ground 44 SW1 - NC, Insert/remove detect for protection 45 +5V O +5V power supply, 300mA /slot 46 SW2 - NC, Insert/remove detect for protection 47 +5V O +5V power supply, 300mA /slot 48 +12V O +12V power supply, 50mA /slot 49 SOUNDIN I Sound input (-5dBm) (used by external sound gener.) 50 -12V O -12V power supply, 50mA /slot SV 738 SPECIFICATIONS Normal Expanded (MSX2) CPU Name: Z80 Frequency: 3.579MHz 3.579 MHz / 6 MHz PRIMARY STORAGE User RAM: 64k 64k (Up to 4MB with mapper) Video RAM: 16k 128k MSX BASIC ROM: 16k 16k+16k MSX BIOS ROM: 16k RS 232 firmware ROM: 8k 8k MSX DOS firmware ROM: 16k 16k (+64k with DOS 2.20) Total internal ROM: 56k 72k (136k with DOS 2.20) Total internal RAM: 80k 192k (384k with 256k mapper) SECONDARY STORAGE Diskdrive Disk: 3.5" Soft sectored Sides: 1 2 Format: CP/M-80 MSX DOS (IBM PC 720k compatible) # of tracks /side: 80 # of tracks /side: 80 # of sectors/track: 17 # of sectors/track: 9 # of bytes/sector: 256 # of bytes/sector: 512 Encoding method: MFM Recording density: 8187 BPI Track density: 135 BPI Formatted capacity: 360k (328k) 720k Unformatted: 500k Rotational speed: 300rpm Data transfer rate: 250 k Bps Seek time: 6/3 mSec Setting time: 15 mSec Motor start time: 400 mSec Average access time: 173/94 mSec Casette (recorder optional) Data transfer rate (baud rate) 1200 BpS (1200Hz - 1 wave "0", 2400Hz - 2 waves "1") 2400 BpS (2400Hz - 1 wave "0", 4800Hz - 2 waves "1") Input (to computer): From earphone terminal of tape recorder Output (from computer): To microphone terminal of tape recorder Synchronization: Asynchronous Modulation: FSK Remote control: Yes (block) DISPLAY Text mode characters: 32*24, 40*24 32*24, 40*24 or 80*26.5 or 80*26.5 Text colours: 2 of 16 of 512 2 of 16 of 512 Graphic resolution: 256*192 512*212 (512*424 interlaced) Graphic colours: 16 of 512 4,16 or 256 of 512 INPUT & OUTPUT PORTS Serial: RS 232 C, 19200 BpS max Paralell: Centronic (Strobed OUTPUT only) Expansion: 34- pin CPU bus Audio/Video: Audio: 3 channel 0-113kHz square output, 4 bit volume control (logarithmic), 15 envelope shapes and 1 square keyklick signal RF and video ports: Composite colour video out (standard) Analog RGB (internal) RF out (standard) Storage: Cassette and disk dirve (+external drive port) Joystick ports: 2, 4bit input, 1bit output, 2bits bidirectional TTL level KEYBOARD Control keys (grey): 20 Cursor movement keys: 4 (enlarged) Charcater keys (white): 49 Total keys: 73 OPERATIVE SYSTEMS (Microsoft) MSX DOS version: 1.03 1.03 or 2.20 Diskbasic version: 1.0 2.0 CP/M-80 version: 2.2 2.2 ************************ End of I/O documentation.