CHRP I/O Device Specification Version 1.0
Change Notice

Table of Contents

, Apple/IBM/Motorola - CHRP BoardThis paper presents a chronological list of all changes approved for the published version of the PowerPC Microprocessor Common Hardware Reference Platform: I/O Device Reference (I/O Device Specification). These changes are approved by the CHRP Board. These changes will be incorporated into the next version of the document at the next printing of the CHRP specification.

SCC Corrections

This Architecture Change Request (ACR00008) was approved by the CHRP Board on June 6, 1996.


Changes are required to document actual Apple SCC registers and their offsets and to clarify the relation between the SCC and the 85C30 chip.


Table 222. Apple SCC Registers (Continued) 
Offset        Register                      Open Firmware Reg Property  
0x000         Command B                                                 
0x010         Data B                                                    
0x020         Command A                                                 
0x030         Data A                                                    
0x040         Channel B Enhancement                                     
0x050         Channel A Enhancement                                     
0x080         SCC Recovery Count                                        
0x090         LTPC Start A                                              
0x0A0         LTPC Start B                                              
0x0B0         LTPC Detect AB                                            
0x100         Timer A                                                   
0x110         Timer B                       reg[1],size=4096            
0x120         Special Character 1A                                      
0x130         Special Character 2A                                      
0x140         Special Character 3A                                      
0x160         Special Detect A                                          
0x180         Special Character 1B                                      
0x190         Special Character 2B                                      
0x1A0         Special Character 3B                                      
0x1C0         Special Detect B                                          
0x1D0         Receive Mask A                                            
0x1E0         Receive Mask B                                            
See Section   Channel A DBDMA Tx Registers  reg[2],size=256             
15.4.1, "Reg                                                            
ister Organi                                                            
zation," on                                                             
page 173                                                                
              Channel A DBDMA Rx Registers  reg[3],size=256             
              Channel B DBDMA Tx Registers  reg[4],size=256             
              Channel B DBDMA Rx Registers  reg[5],size=256             

Table 250. Apple SCC DBDMA Transmit Channel Status Bits (Continued) 
Bit        Meaning                              
s7         1= the timer has decremented to 0;   
           0=the timer is still decrementing    
s6         1=GPIOA is low into the serial       
           port; 0=GPIOA is high                
s5         the LTPC has detected the end of a   
           LocalTalk packet                     
s4 ... s1  not implemented                      
s0         Wait (externally controlled)         
Note: Because this change is extensive, the CHRP board agreed to include it in a update to the PowerPC Microprocessor Common Hardware Reference Platform: I/O Device Reference document. This change will be incorporated in the electronic version during July 1996. This modification will be called Version 1.01.

Delete the special 87308 software implementation note

This Documentation Error Report (DER00001) was approved July 8, 1996.


A Software Implementation Note and compatible property were documented to take care of the case that a National 87308 was used. Analysis of the chip logic indicated they are no longer needed.


UART serial device interrupt definition.

DER00003 was approved by the CHRP Board on July 17, 1996.


Requirement 6-3 requires the UART serial device to generate a low-to-high edge-sensitive interrupt. The legacy UART (16550) actually generates a high-active level interrupt.

Historically, all ISA interrupts were treated as +edge sensitive even though some were +level at the source (this still works). The intent of Requirement 6-3 was to propagate that model, but it didn't come out correctly.


6-3. The UART serial device must generate an interrupt that is compatible with a low-to-high edge sensitive interrupt request input at the interrupt controller.

Detect AB Corrections

ACR00010 was approved by the CHRP Board on July 26, 1996.


Changes are required to resolve ambiguities and inaccuracies in the existing SCC chapter.


"The 2-bit read-only register shown in Table 237 consists of separate Detect A and Detect B bits. They indicate whether the LTPC has detected the abort sequences for the corresponding transmit channels. Both bits are cleared on reset and each bit is set when the LTPC logic has been armed (by setting the Start register) and has then detected the abort sequence. Each bit stays set until the corresponding Start register is cleared by software."

Corrections to ISA Keyboard Mouse

ACR00026 was approved by the CHRP Board on September 23, 1996.


Various typographical errors exist in Chapter 7 which make it appear that the 8042 is not being supported.


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